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MAX7060
280MHz to 450MHz Programmable
ASK/FSK Transmitter
Table 2. Configuration Registers (continued)
REGISTER
FLow0
FLow1
FLoad
EnableReg
DataReg
Status
ADDRESS
0x0D
0x0E
0x0F
0x10
0x11
0x12
BIT 7
flo_15
flo_7
—
—
—
status_7
BIT 6
flo_14
flo_6
—
—
—
status_6
BIT 5
flo_13
flo_5
—
—
—
status_5
BIT 4
flo_12
flo_4
—
—
—
status_4
DATA
BIT 3
flo_11
flo_3
—
—
—
status_3
BIT 2
flo_10
flo_2
—
—
—
status_2
BIT 1
flo_9
flo_1
—
—
—
status_1
BIT 0
flo_8
flo_0
hop
enable
datain
status_0
MODE
R/W
R/W
R/W
R/W
R/W
R
Table 3. Identification (Ident) Register (Address: 0x00)
BIT
7:0
NAME
ident
FUNCTION
Read-only register used for identification purpose. The content of this register is always 0xA6.
Table 4. Configuration 0 (Conf0) Register (Address: 0x01)
BIT
6
5
NAME
gp1bst
pllbw
FUNCTION
0 = Normal GPO1 output driver
1 = Extended driving capability on GPO1
PLL bandwidth setting, low (0) = 300kHz or high (1) = 600kHz; 300kHz is recommended for fractional-N
and 600kHz for fixed-N (ASK mode only)
Control time constants of the analog shaping (bias inductor connected to the ROUT pin)
anshp[1:0]
Rise/fall time
4:3
anshp[1:0]
00
01
10
11
ROUT open-circuited, 4 F s pulse extension present
nominal 3.0 F s rise/fall time
nominal 1.5 F s rise/fall time
no analog shaping, no 4 F s pulse extension
2
1
0
clksby
clkout
mode
Crystal clock output enable (1) while part is in standby mode
Crystal clock output enable (1) on GPO1 output, gp1s[2:0] = 0x2
ASK (0) or FSK (1)
Table 5. Configuration 1 (Conf1) Register
(Address: 0x02)
Table 6. Crystal Divide Settings for Clock
Output
BIT
7:5
4:0
NAME
ckdiv[2:0]
cap[4:0]
FUNCTION
3-bit clock output frequency divider
5-bit capacitor setting
ckdiv[2:0]
000
CRYSTAL FREQUENCY
DIVIDED BY
1
Maxim Integrated
001
010
011
1XX
2
4
8
16
21
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